A digital to analog converter (DAC) receives a digital input and converts the digital input to a piecewise linear output. Digital signals describe values using discrete quantities. Analog signals describe values using continuous quantities. The digital input may be a binary word comprising one or more binary bits, and with each bit having exactly two possible values (e.g., 0 and 1), whereas the piecewise linear output may have 2N possible values, where N is the number bits in the input binary word. The piecewise linear output may be provided in the form of current, voltage, or another quantity. An analog to digital converter (ADC) performs the reverse function of a DAC.
There are many different DAC architectures. No single architecture is optimal for all applications. Considerations in selecting a DAC architecture for design and implementation include size, power, speed, cost, and accuracy. Two of the important parameters characterizing the accuracy of a DAC are integral non-linearity (INL) and differential non-linearity (DNL). Both of these parameters can be expressed in units of least significant bit (LSB), which is the minimum step size of the DAC. For an N-bit DAC, an LSB is equal to 1/(2N). INL error is defined to be the deviation of the DAC's transfer curve from a straight line. DNL error is defined as the variation in analog step sizes away from 1 LSB. The input-output transfer characteristic of a DAC is ideally a straight line implying a linear behavior. In theory, DACs can be designed to have 0 INL and DNL errors. However, due to non-ideal effects such as statistical mismatches in element values, the actual DAC transfer characteristic after implementation is not linear. That is, either or both INL and DNL errors will be greater than 0 LSB. Most signal processing applications require the DAC to meet a certain INL specification. On the other hand, many applications only require the DNL to be less than 1 LSB. DACs having DNL error less than 1 LSB are guaranteed to be monotonic, i.e., as the input code moves in one direction the output will move in the same direction or in the worst case remains flat.
To ensure monotonicity in a binary-weighted DAC, the value of precision conversion elements (e.g., current, resistor, etc.) must be sufficiently precise and have tight tolerances. Random variation in component values can render the DAC's response non-monotonic. Unfortunately, DAC architectures requiring precisely matched components are very expensive to manufacture. On the other hand, an inherently monotonic architecture does not impose any requirement on the matching accuracy of the conversion elements and is therefore inexpensive to implement and mass produce.